Embedded Resistor-Capacitor Film for Fan Out Wafer Level Packaging

ABSTRACT

A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

This application is a divisional application of Ser. No. 15/802,873, filed on Nov. 3, 2017, owned by a common assignee, and herein incorporated by reference in its entirety.

(1) TECHNICAL FIELD

This disclosure is related to wafer packaging technologies, and more particularly, to wafer packaging technologies combining fan out wafer level packaging with printed circuit board/substrate fabrication techniques.

(2) BACKGROUND

Fan out wafer level Package (FO WLP or eWLB) is said to be the future of advanced packaging. This type of package is illustrated in FIG. 1. SiP (System in Package) is another advanced packaging solution that can integrate multiple chips and active and passive discrete components using a substrate interposer 10, as shown in FIG. 2, where the die 20 is integrated with passive components such as resistors 42 and capacitors 44 and other active components. A disadvantage of SiP is that the substrate material will add to the total thickness of the package. The FO WLP package allows more units per wafer and the final package thickness will be thinner. The current FO WLP available in the industry is a single die packaging.

U.S. Patent Applications 2017/0170031 (Li et al) and 2017/0287856 (Lee et al) disclose various fan out wafer level packages. U.S. Pat. No. 9,779,880 (Chang et al) shows an embedded capacitor fabrication.

SUMMARY

It is the primary objective of the present disclosure to provide an embedded film resistor-capacitor fan out (EfRC-FO) package.

It is another objective of the disclosure to provide a packaging process that combines SIP and eWLB with embedded resistor and capacitor technology.

In accordance with the objectives of the present disclosure, a panel type fan-out wafer level package with embedded film type capacitors and resistors is achieved. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

Also in accordance with the objectives of the present disclosure, a method to fabricate a panel type fan out wafer level package with embedded film type capacitors and resistors is achieved. Copper posts are formed on a top side of a silicon wafer. The silicon wafer is singulated into a plurality of silicon dies. A plurality of silicon dies are reconstituted onto a panel and encapsulated with a molding compound on top and lateral sides. Thereafter, the panel is ground to expose the copper posts. Through-mold vias are opened through the molding compound outside of the silicon dies. The through-mold vias are filled with a conducting layer. Interconnecting layers are built up comprising: forming at least one redistribution layer connected to the silicon die through the copper posts and connected to the conducting layer in the through-mold vias, laminating at least one embedded capacitor material (ECM) sheet onto package, and laminating at least one embedded resistor-conductor material (RCM) sheet onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected. Metal plates are formed on a bottom side of the panel electrically contacting the through-mold via conducting layer. Solder balls are attached to the metal plates. The panel is singulated to form completed packages.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of this description, there is shown:

FIG. 1 is a cross-sectional representation of a fan out wafer level package of the prior art.

FIG. 2 is a cross-sectional representation of a system in package of the prior art.

FIG. 3 is a cross-sectional representation of an embedded capacitor material (ECM) structure of the present disclosure.

FIG. 4 is a cross-sectional representation of a resistor-conductor material (RCM) structure of the present disclosure.

FIG. 5 is a flow chart of a first process of the present disclosure.

FIG. 6 is a cross-sectional representation of the package after the first process of the present disclosure.

FIG. 7 is a flow chart of a second process of the present disclosure.

FIG. 8 is a cross-sectional representation of the package after the second process of the present disclosure.

FIG. 9 is a flow chart of a third process of the present disclosure.

FIGS. 10-14 are cross-sectional representations of steps in the third process of the present disclosure.

FIG. 15 is a flow chart of a fourth process of the present disclosure.

FIG. 16 is a cross-sectional representation of the completed package of the present disclosure.

DETAILED DESCRIPTION

The present disclosure combines FO WLP and SiP with the use of embedding film technology of resistors and capacitors for an improved package design. Thin film capacitors (ECM—embedded capacitor material) and resistors (RCM—Resistor-Conductor Material) have been used in substrate processing using standard lamination and photo processing techniques. Embedding the resistor and capacitor in a thin film results in a super thin form factor.

Other advantages of FO WLP SiP embedded with ECM & RCM film include:

1. Save significant real estate surface area.

2. Less parasitic inductance than discrete components (noise and EMI reduction) because of shorter routing between components and die.

3. Elimination of solder joints thus improves reliability of resistors and capacitors.

4. Enhance electrical performance with shorter leads and closer component placement.

5. Cost benefit since embedded passives are made by mass formation rather than mounting each individual component.

6. Less complex material inventory management than a magnitude of surface mount technology (SMT) type discrete passive components.

7. Can allow existing chips to be SiP with other available components rather than designing a new system on chip (SoC). This allows a faster time to market for a new design.

In the present disclosure, we propose to integrate a die of PMU (Power management unit), bluetooth, or MCU (microcontroller unit) through a hybrid panel based process (i.e. combination of FO WLP processing and PCB/Substrate Fabrication Techniques). This will enable a reduced size SIP package solution with the use of embedded film type resistors and capacitors.

Fabricating the FO WLP begins with wafer preparation (Cu post) and continues with reconstitution (die face up) and overmolding into a panel. Through mold via (TMV) is necessary to be able to achieve the vertical interconnect from the bottom land side to the redistribution layer (RDL) routing. Once the panel has the TMV and first RDL connected from the die Cu post, the build up of succeeding RDL, ECM and RCM is an additive process.

The ECM and RCM will be available in sheets and will be built up in between the dielectric polymer (PI—Polyimide). The ECM and RCM will be patterned (photo imaged), etched and laminated like standard PCB fabrication techniques. The structure can include multiples of RDL, ECM and RCM layers depending on the build up.

The standard FO WLP consists of one die 20 that will be reconstituted (either face up or face down) in plastic molding 28 with RDL 12 (FIG. 2). In the package of the present disclosure, in addition to the FO WLP (chip first and face-up), TMV (Through mold via) and embedded film substrate processing are required.

There are various ECM manufacturers in the market for the embedded capacitor material, including 3M, Sanmina, DuPont and Shipley while OhmegaPly is a manufacturer of resistor-conductor material (RCM). As illustrated in FIG. 3, an ECM is made of a very thin layer of ceramic-filled epoxy 100, about 3 to 19 μm, sandwiched between two layers of 17 μm or 35 μm copper foil 102, 104 with a total thickness of 37 μm to 89 μm.

As shown in FIG. 4, OhmegaPly RCM is a Nickel Phosphorous (NiP) metal alloy 110 that is electrodeposited on the copper foil 112 with overall thickness of 9 μm to 36 μm depending on the Cu thickness and NiP plating/resistance requirement. The RCM is then laminated to a dielectric material 114 on copper foil 116.

Since the ECM and RCM can be patterned (photoimaged and etched), they can satisfy various geometry requirements as different sizes of capacitors and resistors. Capacitance and resistivity will be dependent on the sheet thickness and surface area of the substrate films.

The embedded film resistor-capacitor fan out (EfRC-FO) package design of the present disclosure comprises four processing groups: 1) Wafer Preparation (Cu Post), 2) Reconstitution to panel, 3) Fan-out with RDL, ECM & RCM and 4) Backend Assembly finishing.

Referring now to FIGS. 5-16, the process of fabricating a package of the present disclosure will be described in detail. FIG. 5 is a flow chart of the steps in the first process of the fabrication, the results of which are shown in FIG. 6.

Wafer Preparation is the formation of copper posts or studs on the native wafer using standard wafer-level chip scale processing (WLCSP). Once the copper post is formed, the wafer will then be thinned and diced. The diced wafer will provide PMU (Power management unit), bluetooth, MCU (microcontroller unit) dies, and any other application specific integrated circuits (ASIC). Referring now to FIGS. 5 and 6, wafer 50 is coated with a polymer 52, in step 151. In step 152, the polymer is developed, exposed, and cured, wherein openings are made through the polymer to the pads 54 on the die.

In step 153, a seed layer, not shown, is deposited over the polymer layer and within the polymer openings. Preferably, the seed layer will be titanium or copper.

Now, in step 154, a photoresist mask is formed with openings where copper posts are to be placed. Copper posts 56 are plated onto the seed layer in the openings in step 155, as shown in FIG. 6. In step 156, the mask is stripped and the seed layer not covered by the copper is etched away.

Next, in step 157, the bottom side of the wafer 50 is ground away until a pre-determined portion of the wafer 50 has been removed. Grinding is performed to meet the total package height thickness requirement as well as to improve the warpage of the package and process and assembly handling during subsequent process steps. Finally in step 158, the wafer is sawed and singulated into individual dies.

Referring to the flowchart in FIG. 7 and the cross-section in FIG. 8, the second process of reconstitution to a panel is performed. In step 171, a plurality of dies 50 are attached to a carrier, not shown. In step 172, a molding compound 92 is coated on the top side of the die, encapsulating the die and copper pillars. The die is molded or encapsulated by a compression method using mold granular epoxy resin material with a fine filler to serve as the mold underfill. For example, the molding 92 is cured at about 175° C. for about 120 seconds. The molding thickness is preferably about 150 to 1000 μm. To finish cross-linking, the molding is post-cured (PMC) at about 175° C. for about 6 hours. The plurality of dies covered with the molding compound form the panel.

Now the front side (top in FIG. 8) is ground to expose the tops of the copper posts 56, as shown in FIG. 8. The panel is removed from the carrier. Now the panel is ready for the fan-out process.

Referring now to FIGS. 9-14, the third process of the present disclosure will be described. The fan-out process starts with dielectric coating and through mold via (TMV) to provide vertical interconnection. The build-up (additive) process will follow with the RDL, ECM and RCM layers. As shown in FIG. 9, the first step 201 is to coat a polymer layer 302 on the top surface of the molded die 50.

The polymer material may be polyimide, coated to a thickness of between about 7-9 μm, as shown in FIG. 10. The polymer 302 is patterned to form openings over the copper posts 56 and to form openings where through mold vias (TMV) are to be formed outside of the die. After patterning, the polymer is cured.

Next in step 202, TMV's 304 are etched through openings in the polymer 302 all the way through the molding compound 92 to provide vias 304 opening to both the top and bottom sides of the package. TMV's 304 are shown in FIG. 10.

In step 203, a seed layer 306 is deposited over the polymer layer 302 and within the TMV and openings to the copper pillars. Now a photoresist mask, not shown, is formed to provide openings to the TMV's and to areas where the resdistribution layer (RDL) is to be formed.

In step 204, as shown in FIG. 11, copper 308 is plated on the seed layer, filling the TMV's and forming the redistribution layer (RDL) 309. The photoresist mask is stripped and the seed layer etched away where it is not covered by the copper layer.

In step 205, polymer 310 is coated over the polymer 304 and RDL layer 309, as shown in FIG. 12.

The ECM and RCM are available in sheets and can be patterned and etched before they are laminated into the package. Steps 210 constitute the ECM process. In step 211, the polymer layer 310 is patterned to provide openings to the RDL layer 309. Copper is plated into the openings, photoresist is stripped, and seed layer etched away to provide RDL connection 311 for the ECM.

The ECM sheet comprises epoxy 314 and copper foil layers on bottom 312 and top 316. In step 212, the top and bottom copper layers of the ECM sheet, formed as shown in FIG. 3, are now patterned to form the capacitors, as shown in FIG. 12, using photoprocess, strip, and etch steps. Next, in step 213, the patterned ECM sheet is laminated onto the panel and electrically connected through the RDL pattern 311.

Next, in step 215, another polymer layer 318 is coated over the ECM, as shown in FIG. 13. Steps 220 constitute the RCM process. In step 221, the polymer layer 318 is patterned to provide openings to the top copper layer 316 of the ECM sheet. Copper is plated into the openings, photoresist is stripped, and seed layer etched away to provide RDL connection 322 between the RCM and the ECM.

The RCM sheet comprises bottom copper layer 319, dielectric 320, NiP layer 324, and top copper layer 326. In step 222, the RCM sheet is laminated onto the panel and electrically connected through the RDL pattern 322 to the top copper layer of the ECM sheet, as shown in FIG. 13. In step 223, using photoprocess, strip, and etch steps, the top copper layer 326 and NiP layer 324 of the RCM sheet are patterned. Alternatively, these layers may be patterned to form individual resistors prior to lamination.

The ECM and RCM sheets may be laminated onto the panel in any order and there may be multiple buildup layers, depending on package requirements.

The top side and bottom side metal layers of the package can be formed through the RDL process. The topside and bottom will have protection using either Polyimide or solder mask, as shown in FIG. 14. In step 225, polyimide 328 and/or solder mask 330 are coated over the top of the panel.

In step 226, the panel is flipped and a solder mask or polyimide 332 is coated over the bottom surface of the panel. The bottom mask layer 332 is patterned using a photoresist mask to provide openings for solder bump attachment. In step 227, metal 334 is plated into the openings through the solder mask 332. In step 228, the photoresist mask is stripped and excess metal is etched away.

The panel is now ready for the Backend Assembly finishing steps, illustrated in the flowchart in FIG. 15 and in cross-section in FIG. 16. In step 401, solder balls 400 are attached to the panel onto the metal plates 334. In step 402, the wafer is sawed and singulated, and loaded in a tray (step 403) for final visual inspection (step 404) and final test (step 405). Finally the completed packages will be ready for pack and ship (step 406).

FIG. 16 shows the completed package. The silicon chip 50, encapsulated by molding compound 92, contacts solder mask 332 at the bottom of the package. Connecting to the top of the silicon chip through copper posts 56 are fan-out redistribution layers 309, 311, 322 and embedded capacitors (312/314/316) and resistors (319/320/324/326) under a top polyimide or solder mask 330. The RDL, capacitors, and resistors are all electrically interconnected. The RDL, capacitors, and resistors are electrically connected to the solder balls 400 through the TMV's 308.

Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims. 

What is claimed is:
 1. A method of fabricating a panel type fan out wafer level package with embedded film type capacitors and resistors comprising: forming copper posts on a top side of a silicon wafer; singulating said silicon wafer into a plurality of silicon dies; reconstituting said plurality of silicon dies onto a panel and encapsulating said plurality of silicon dies with a molding compound on top and lateral sides; thereafter grinding said panel to expose said copper posts; thereafter building up interconnecting layers comprising: forming at least one redistribution layer connected to said silicon dies through said copper posts; laminating at least one embedded capacitor material (ECM) sheet onto said package; and laminating at least one embedded resistor-conductor material (RCM) sheet onto said package wherein said at least one redistribution layer, capacitors in said at least one ECM, and resistors in said at least one RCM are electrically interconnected; forming metal plates on a bottom side of said panel; attaching solder balls to said metal plates; and singulating said panel to form completed packages.
 2. The method according to claim 1 wherein said at least one ECM sheet comprises a ceramic-filled epoxy layer sandwiched between two copper foil layers.
 3. The method according to claim 1 wherein said at least one RCM sheet comprises a nickel phosphorus layer laminated to an overlying first copper foil layer and to an underlying dielectric layer wherein said dielectric layer is laminated to an underlying second copper foil layer.
 4. The method according to claim 1 wherein said at least one redistribution layer comprises copper.
 5. The method according to claim 1 further comprising: opening through-mold vias through said molding compound outside of said silicon die; filling said through-mold vias with a copper layer; and interconnecting said at least one redistribution layer to solder balls attached on a bottom surface of said package through said copper layer.
 6. The method according to claim 1 wherein said at least one ECM sheet and said at least one RCM sheet are laminated onto said package in any order.
 7. The method according to claim 1 wherein a plurality of redistribution layers, a plurality of ECM sheets, and a plurality of RCM sheets are added to said package in any order.
 8. A method of fabricating a panel type fan out wafer level package with embedded film type capacitors and resistors comprising: forming copper posts on a top side of a silicon wafer; singulating said silicon wafer into a plurality of silicon dies; reconstituting said plurality of silicon dies onto a panel and encapsulating said plurality of silicon dies with a molding compound on top and lateral sides; thereafter grinding said panel to expose said copper posts; opening through-mold vias through said molding compound outside of said silicon dies; filling said through-mold vias with a conducting layer; thereafter building up interconnecting layers comprising: forming at least one redistribution layer connected to said silicon dies through said copper posts and connected to said conducting layer in said through-mold vias; laminating at least one embedded capacitor material (ECM) sheet onto said package wherein said at least one ECM sheet comprises a ceramic-filled epoxy layer sandwiched between two copper foil layers; and laminating at least one embedded resistor-conductor material (RCM) sheet onto said package wherein said at least one RCM sheet comprises a nickel phosphorus layer laminated to an overlying first copper foil layer and to an underlying dielectric layer wherein said dielectric layer is laminated to an underlying second copper foil layer and wherein said at least one redistribution layer, capacitors in said at least one ECM, and resistors in said at least one RCM are electrically interconnected; forming metal plates on a bottom side of said panel electrically contacting said through-mold via conducting layer; attaching solder balls to said metal plates; and singulating said panel to form completed packages.
 9. The method according to claim 8 wherein said at least one redistribution layer comprises copper.
 10. The method according to claim 8 wherein said at least one ECM sheet and said at least one RCM sheet are laminated onto said package in any order.
 11. The method according to claim 8 wherein a plurality of redistribution layers, a plurality of ECM sheets, and a plurality of RCM sheets are added to said package in any order.
 12. The method according to claim 8 wherein said conducting layer comprises copper.
 13. A method of fabricating a panel type fan out wafer level package with embedded film type capacitors and resistors comprising: forming copper posts on a top side of a silicon wafer; singulating said silicon wafer into a plurality of silicon dies; reconstituting said plurality of silicon dies onto a panel and encapsulating said plurality of silicon dies with a molding compound on top and lateral sides; thereafter grinding said panel to expose said copper posts; opening through-mold vias through said molding compound outside of said silicon dies; filling said through-mold vias with a conducting layer; thereafter building up interconnecting layers comprising: forming at least one redistribution layer connected to said silicon dies through said copper posts and connected to said conducting layer in said through-mold vias; laminating at least one embedded capacitor material (ECM) sheet onto said package wherein said at least one ECM sheet comprises a ceramic-filled epoxy layer sandwiched between two copper foil layers; and laminating at least one embedded resistor-conductor material (RCM) sheet onto said package wherein said at least one RCM sheet comprises a nickel phosphorus layer laminated to an overlying first copper foil layer and to an underlying dielectric layer wherein said dielectric layer is laminated to an underlying second copper foil layer and wherein said at least one redistribution layer, capacitors in said at least one ECM, and resistors in said at least one RCM are electrically interconnected; forming a topside solder protection mask on a top surface of said package and a bottomside solder protection mask on a bottom surface of said package wherein said bottomside solder protection mask coats an entire bottom side of said silicon dies; forming metal plates on said bottom side of said panel through openings in said bottomside solder protection mask electrically contacting said through-mold via conducting layer; attaching solder balls to said metal plates; and singulating said panel to form completed packages.
 14. The method according to claim 13 wherein said at least one redistribution layer comprises copper.
 15. The method according to claim 13 wherein said at least one ECM sheet and said at least one RCM sheet are laminated onto said package in any order.
 16. The method according to claim 13 wherein a plurality of redistribution layers, a plurality of ECM sheets, and a plurality of RCM sheets are added to said package in any order.
 17. The method according to claim 13 wherein said conducting layer comprises copper. 